Ada 83 on AVR microcontrollers
The famous Arduino Uno uses an Atmel ATMEGA 328P chip. The base module for 328P register map can be conveniently expressed by a record type and its representation clause.
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-- CC BY SA ATMEGA_328P.ADS VINCENT MORIN 23/3/2025 UNIVERSITE DE BRETAGNE OCCIDENTALE
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-- 1 2 3 4 5 6 7 8 9 0 1 2
with TYPES;
use TYPES;
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package ATMEGA_328P
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is
type RAM_MAP is record
-- -----------------------------------------------------------------------------
-- PAGE 534 NOTICE 8271B-AVR
-- -----------------------------------------------------------------------------
PIN_B, DDR_B, PORT_B : BYTE;
PIN_C, DDR_C, PORT_C : BYTE;
PIN_D, DDR_D, PORT_D : BYTE;
TIFR0_OCF0A, TIFR0_OCF0B, TIFR0_TOV0 : BOOLEAN;
TIFR1_ICF1,
TIFR1_OCF1A, TIFR1_OCF1B, TIFR1_TOV1 : BOOLEAN;
TIFR2_OCF2A, TIFR2_OCF2B, TIFR2_TOV2 : BOOLEAN;
PCIFR : U3;
-- -----------------------------------------------------------------------------
-- PAGE 533 NOTICE 8271B-AVR
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EIFR_INTF,
EIMSK_INT : U2;
GPIOR0 : U8;
EECR_EEPM : U2;
EECR_EERIE, EECR_EEMPE, EECR_EEPE,
EECR_EERE : BOOLEAN;
EEDR : U8;
EEAR : U16;
GTCCR_TSM, GTCCR_PSRASY, GTCCR_PSRSYNC : BOOLEAN;
TCCR0A_COM0A, TCCR0A_COM0B, TCCR0A_WGM : U2;
TCCR0B_WGM : BOOLEAN;
TCCR0B_CS : U3;
TCCR0B_FOC0A, TCCR0B_FOC0B : BOOLEAN;
TCNT0,
OCR0A,
OCR0B : U8;
GPIOR1, GPIOR2 : U8;
SPCR_SPIE, SPCR_SPE, SPCR_DORD,
SPCR_MSTR, SPCR_CPOL, SPCR_CPHA : BOOLEAN;
SPCR_SPR : U2;
SPSR_SPIF, SPSR_WCOL, SPSR_SPI2X : BOOLEAN;
SPDR : U8;
ACSR_ACD, ACSR_ACBG, ACSR_ACO, ACSR_ACI,
ACSR_ACIE, ACSR_ACIC : BOOLEAN;
ACSR_ACIS : U2;
SMCR_SM : U3;
SMCR_SE : BOOLEAN;
MCUSR_WDRF, MCUSR_BORF, MCUSR_EXTRF,
MCUSR_PORF : BOOLEAN;
MCUCR_BODS, MCUCR_BODSE, MCUCR_PUD,
MCUCR_IVSEL, MCUCR_IVCE : BOOLEAN;
SPMCSR_SPMIE, SPMCSR_RWWSB,
SPMCSR_RWWSRE, SPMCSR_BLBSET,
SPMCSR_PGWRT, SPMCSR_PGERS,
SPMCSR_SELFPRGEN : BOOLEAN;
SP : U11;
SREG_I, SREG_T, SREG_H, SREG_S,
SREG_V, SREG_N, SREG_Z, SREG_C : BOOLEAN;
WDTCSR_WDIF, WDTCSR_WDIE, WDTCSR_WDP3,
WDTCSR_WDCE, WDTCSR_WDE : BOOLEAN;
WDTCSR_WDP : U3;
CLKPR_CLKPCE : BOOLEAN;
CLKPR_CLKPS : U4;
PRR_PRTWI, PRR_PRTIM2, PRR_PRTIM0,
PRR_PRTIM1, PRR_PRSPI, PRR_PRUSART0,
PRR_PRADC : BOOLEAN;
OSCCAL : U8;
PCICR_PCIE : U3;
EICRA_ISC1, EICRA_ISC0 : U2;
PCMSK0_PCINT, PCMSK1_PCINT, PCMSK2_PCINT : U8;
TIMSK0_OCIE0B,
TIMSK0_OCIE0A, TIMSK0_TOIE0 : BOOLEAN;
TIMSK1_ICIE1, TIMSK1_OCIE1B,
TIMSK1_OCIE1A, TIMSK1_TOIE1 : BOOLEAN;
TIMSK2_OCIE2B,
TIMSK2_OCIE2A, TIMSK2_TOIE2 : BOOLEAN;
ADC : U16;
ADCSRA_ADEN, ADCSRA_ADSC,
ADCSRA_ADATE, ADCSRA_ADIF,
ADCSRA_ADIE, ADMUX_ADLAR,
ADCSRB_ACME : BOOLEAN;
ADCSRA_ADPS, ADCSRB_ADTS : U3;
ADMUX_REFS : U2;
ADMUX_MUX : U4;
-- -----------------------------------------------------------------------------
-- PAGE 532 NOTICE 8271B-AVR
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DIDR0_ADC5D, DIDR0_ADC4D, DIDR0_ADC3D,
DIDR0_ADC2D, DIDR0_ADC1D, DIDR0_ADC0D : BOOLEAN;
DIDR1_AIN1D, DIDR1_AIN0D : BOOLEAN;
TCCR1A_COM1A, TCCR1A_COM1B, TCCR1A_WGM : U2;
TCCR1B_ICNC1, TCCR1B_ICES1 : BOOLEAN;
TCCR1B_WGM : U2;
TCCR1B_CS : U3;
TCCR1C_FOC1A, TCCR1C_FOC1B : BOOLEAN;
TCNT1, ICR1, OCR1A, OCR1B : U16;
TCCR2A_COM2A, TCCR2A_COM2B, TCCR2A_WGM : U2;
TCCR2B_WGM : BOOLEAN;
TCCR2B_CS : U3;
TCCR2B_FOC2A, TCCR2B_FOC2B : BOOLEAN;
TCNT2, OCR2A, OCR2B : U8;
ASSR_EXCLK, ASSR_AS2, ASSR_TCN2UB,
ASSR_OCR2AUB, ASSR_OCR2BUB,
ASSR_TCR2AUB, ASSR_TCR2BUB : BOOLEAN;
TWBR : U8;
TWSR_TWS : U5;
TWSR_TWPS : U2;
TWAR_TWA : U7;
TWAR_TWGCE : BOOLEAN;
TWDR : U8;
TWCR_TWINT, TWCR_TWEA, TWCR_TWSTA,
TWCR_TWSTO, TWCR_TWWC, TWCR_TWEN,
TWCR_TWIE : BOOLEAN;
TWAMR_TWAM : U7;
-- -----------------------------------------------------------------------------
-- PAGE 531 NOTICE 8271B-AVR
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UCSR0A_RXC0, UCSR0A_TXC0, UCSR0A_UDRE0,
UCSR0A_FE0, UCSR0A_DOR0, UCSR0A_UPE0,
UCSR0A_U2X0, UCSR0A_MPCM0 : BOOLEAN;
UCSR0B_RXCIE0, UCSR0B_TXCIE0,
UCSR0B_UDRIE0, UCSR0B_RXEN0,
UCSR0B_TXEN0, UCSR0B_UCSZ02,
UCSR0B_RXB80, UCSR0B_TXB80 : BOOLEAN;
UCSR0C_UMSEL0, UCSR0C_UPM0,
UCSR0C_UCSZ0 : U2;
UCSR0C_USBS0, UCSR0C_UCPOL0 : BOOLEAN;
UBRR : U12;
UDR0 : U8;
end record;
for RAM_MAP use
record at mod 1;
-- -----------------------------------------------------------------------------
-- PAGE 534 NOTICE 8271B-AVR
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-- 16#23# .. 16#2B#
PIN_B at 16#23# range 0..7;
DDR_B at 16#24# range 0..7;
PORT_B at 16#25# range 0..7;
PIN_C at 16#26# range 0..7;
DDR_C at 16#27# range 0..7;
PORT_C at 16#28# range 0..7;
PIN_D at 16#29# range 0..7;
DDR_D at 16#2A# range 0..7;
PORT_D at 16#2B# range 0..7;
-- 16#35#
TIFR0_OCF0A at 16#35# range 1..1; TIFR0_OCF0B at 16#35# range 2..2;
TIFR0_TOV0 at 16#35# range 0..0;
-- 16#36#
TIFR1_ICF1 at 16#36# range 5..5; TIFR1_OCF1A at 16#36# range 1..1;
TIFR1_OCF1B at 16#36# range 2..2; TIFR1_TOV1 at 16#36# range 0..0;
-- 16#37#
TIFR2_OCF2A at 16#37# range 1..1; TIFR2_OCF2B at 16#37# range 2..2;
TIFR2_TOV2 at 16#37# range 0..0;
-- 16#3B#
PCIFR at 16#3B# range 0..2;
-- -----------------------------------------------------------------------------
-- PAGE 533 NOTICE 8271B-AVR
-- -----------------------------------------------------------------------------
-- 16#3C#
EIFR_INTF at 16#3C# range 0..1;
-- 16#3D#
EIMSK_INT at 16#3D# range 0..1;
-- 16#3E#
GPIOR0 at 16#3E# range 0..7;
-- 16#3F#
EECR_EEPM at 16#3F# range 4..5; EECR_EERIE at 16#3F# range 3..3;
EECR_EEMPE at 16#3F# range 2..2; EECR_EEPE at 16#3F# range 1..1;
EECR_EERE at 16#3F# range 0..0;
-- 16#40#
EEDR at 16#40# range 0..7;
-- 16#41#
EEAR at 16#41# range 0..15;
-- 16#43#
GTCCR_TSM at 16#43# range 7..7; GTCCR_PSRASY at 16#43# range 1..1;
GTCCR_PSRSYNC at 16#43# range 0..0;
-- 16#44#
TCCR0A_COM0A at 16#44# range 6..7; TCCR0A_COM0B at 16#44# range 4..5;
TCCR0A_WGM at 16#44# range 0..1;
-- 16#45#
TCCR0B_FOC0A at 16#45# range 7..7; TCCR0B_FOC0B at 16#45# range 6..6;
TCCR0B_WGM at 16#45# range 3..3; TCCR0B_CS at 16#45# range 0..2;
-- 16#46#
TCNT0 at 16#46# range 0..7;
-- 16#47#
OCR0A at 16#47# range 0..7;
-- 16#48#
OCR0B at 16#48# range 0..7;
-- 16#4A#
GPIOR1 at 16#4A# range 0..7;
-- 16#4B#
GPIOR2 at 16#4B# range 0..7;
-- 16#4C#
SPCR_SPIE at 16#4C# range 7..7; SPCR_SPE at 16#4C# range 6..6;
SPCR_DORD at 16#4C# range 5..5; SPCR_MSTR at 16#4C# range 4..4;
SPCR_CPOL at 16#4C# range 3..3; SPCR_CPHA at 16#4C# range 2..2;
SPCR_SPR at 16#4C# range 0..1;
-- 16#4D#
SPSR_SPIF at 16#4D# range 7..7; SPSR_WCOL at 16#4D# range 6..6;
SPSR_SPI2X at 16#4D# range 0..0;
-- 16#4E#
SPDR at 16#4E# range 0..7;
-- 16#50#
ACSR_ACD at 16#50# range 7..7; ACSR_ACBG at 16#50# range 6..6;
ACSR_ACO at 16#50# range 5..5; ACSR_ACI at 16#50# range 4..4;
ACSR_ACIE at 16#50# range 3..3; ACSR_ACIC at 16#50# range 2..2;
ACSR_ACIS at 16#50# range 0..1;
-- 16#53#
SMCR_SM at 16#53# range 1..3;
SMCR_SE at 16#53# range 0..0;
-- 16#54#
MCUSR_WDRF at 16#54# range 3..3; MCUSR_BORF at 16#54# range 2..2;
MCUSR_EXTRF at 16#54# range 1..1; MCUSR_PORF at 16#54# range 0..0;
-- 16#55#
MCUCR_BODS at 16#55# range 6..6; MCUCR_BODSE at 16#55# range 5..5;
MCUCR_PUD at 16#55# range 4..4; MCUCR_IVSEL at 16#55# range 1..1;
MCUCR_IVCE at 16#55# range 0..0;
-- 16#57#
SPMCSR_SPMIE at 16#57# range 7..7; SPMCSR_RWWSB at 16#57# range 6..6;
SPMCSR_RWWSRE at 16#57# range 4..4; SPMCSR_BLBSET at 16#57# range 3..3;
SPMCSR_PGWRT at 16#57# range 2..2; SPMCSR_PGERS at 16#57# range 1..1;
SPMCSR_SELFPRGEN at 16#57# range 0..0;
-- 16#5D#
SP at 16#5D# range 0..10;
-- 16#5F#
SREG_I at 16#5F# range 7..7; SREG_T at 16#5F# range 6..6;
SREG_H at 16#5F# range 5..5; SREG_S at 16#5F# range 4..4;
SREG_V at 16#5F# range 3..3; SREG_N at 16#5F# range 2..2;
SREG_Z at 16#5F# range 1..1; SREG_C at 16#5F# range 0..0;
-- 16#60#
WDTCSR_WDIF at 16#60# range 7..7; WDTCSR_WDIE at 16#60# range 6..6;
WDTCSR_WDP3 at 16#60# range 5..5; WDTCSR_WDCE at 16#60# range 4..4;
WDTCSR_WDE at 16#60# range 3..3; WDTCSR_WDP at 16#60# range 0..2;
-- 16#61#
CLKPR_CLKPCE at 16#61# range 7..7;
CLKPR_CLKPS at 16#61# range 0..3;
-- 16#64#
PRR_PRTWI at 16#64# range 7..7; PRR_PRTIM2 at 16#64# range 6..6;
PRR_PRTIM0 at 16#64# range 5..5; PRR_PRTIM1 at 16#64# range 3..3;
PRR_PRSPI at 16#64# range 2..2; PRR_PRUSART0 at 16#64# range 1..1;
PRR_PRADC at 16#64# range 0..0;
-- 16#66#
OSCCAL at 16#66# range 0..7;
-- 16#68#
PCICR_PCIE at 16#68# range 0..2;
-- 16#69#
EICRA_ISC1 at 16#69# range 2..3; EICRA_ISC0 at 16#69# range 0..1;
-- 16#6B#
PCMSK0_PCINT at 16#6B# range 0..7;
-- 16#6C#
PCMSK1_PCINT at 16#6C# range 0..7;
-- 16#6D#
PCMSK2_PCINT at 16#6D# range 0..7;
-- 16#6E#
TIMSK0_OCIE0B at 16#6E# range 2..2; TIMSK0_OCIE0A at 16#6E# range 1..1;
TIMSK0_TOIE0 at 16#6E# range 0..0;
-- 16#6F#
TIMSK1_ICIE1 at 16#6F# range 5..5;
TIMSK1_OCIE1B at 16#6F# range 2..2; TIMSK1_OCIE1A at 16#6F# range 1..1;
TIMSK1_TOIE1 at 16#6F# range 0..0;
-- 16#70#
TIMSK2_OCIE2B at 16#70# range 2..2; TIMSK2_OCIE2A at 16#70# range 1..1;
TIMSK2_TOIE2 at 16#70# range 0..0;
-- 16#78#
ADC at 16#78# range 0..15;
-- 16#7A#
ADCSRA_ADEN at 16#7A# range 7..7; ADCSRA_ADSC at 16#7A# range 6..6;
ADCSRA_ADATE at 16#7A# range 5..5; ADCSRA_ADIF at 16#7A# range 4..4;
ADCSRA_ADIE at 16#7A# range 3..3; ADCSRA_ADPS at 16#7A# range 0..2;
-- 16#7B#
ADCSRB_ACME at 16#7B# range 6..6; ADCSRB_ADTS at 16#7B# range 0..2;
-- 16#7C#
ADMUX_REFS at 16#7C# range 6..7; ADMUX_ADLAR at 16#7C# range 5..5;
ADMUX_MUX at 16#7C# range 0..3;
-- -----------------------------------------------------------------------------
-- PAGE 532 NOTICE 8271B-AVR
-- -----------------------------------------------------------------------------
-- 16#7E#
DIDR0_ADC5D at 16#7E# range 5..5; DIDR0_ADC4D at 16#7E# range 4..4;
DIDR0_ADC3D at 16#7E# range 3..3; DIDR0_ADC2D at 16#7E# range 2..2;
DIDR0_ADC1D at 16#7E# range 1..1; DIDR0_ADC0D at 16#7E# range 0..0;
-- 16#7F#
DIDR1_AIN1D at 16#7F# range 1..1; DIDR1_AIN0D at 16#7F# range 0..0;
-- 16#80#
TCCR1A_COM1A at 16#80# range 6..7; TCCR1A_COM1B at 16#80# range 4..5;
TCCR1A_WGM at 16#80# range 0..1;
-- 16#81#
TCCR1B_ICNC1 at 16#81# range 7..7; TCCR1B_ICES1 at 16#81# range 6..6;
TCCR1B_WGM at 16#81# range 3..4; TCCR1B_CS at 16#81# range 0..2;
-- 16#82#
TCCR1C_FOC1A at 16#82# range 7..7; TCCR1C_FOC1B at 16#82# range 6..6;
-- 16#84#
TCNT1 at 16#84# range 0..15;
-- 16#86#
ICR1 at 16#86# range 0..15;
-- 16#88#
OCR1A at 16#88# range 0..15;
-- 16#8A#
OCR1B at 16#8A# range 0..15;
-- 16#B0#
TCCR2A_COM2A at 16#B0# range 6..7; TCCR2A_COM2B at 16#B0# range 4..5;
TCCR2A_WGM at 16#B0# range 0..1;
-- 16#B1#
TCCR2B_FOC2A at 16#B1# range 7..7; TCCR2B_FOC2B at 16#B1# range 6..6;
TCCR2B_WGM at 16#B1# range 3..3; TCCR2B_CS at 16#B1# range 0..2;
-- 16#B2#
TCNT2 at 16#B2# range 0..7;
-- 16#B3#
OCR2A at 16#B3# range 0..7;
-- 16#B4#
OCR2B at 16#B4# range 0..7;
-- 16#B6#
ASSR_EXCLK at 16#B6# range 6..6; ASSR_AS2 at 16#B6# range 5..5;
ASSR_TCN2UB at 16#B6# range 4..4; ASSR_OCR2AUB at 16#B6# range 3..3;
ASSR_OCR2BUB at 16#B6# range 2..2; ASSR_TCR2AUB at 16#B6# range 1..1;
ASSR_TCR2BUB at 16#B6# range 0..0;
-- 16#B8#
TWBR at 16#B8# range 0..7;
-- 16#B9#
TWSR_TWS at 16#B9# range 3..7;
TWSR_TWPS at 16#B9# range 0..1;
-- 16#BA#
TWAR_TWA at 16#BA# range 1..7;
TWAR_TWGCE at 16#BA# range 0..0;
-- 16#BB#
TWDR at 16#BB# range 0..7;
-- 16#BC#
TWCR_TWINT at 16#BC# range 7..7; TWCR_TWEA at 16#BC# range 6..6;
TWCR_TWSTA at 16#BC# range 5..5; TWCR_TWSTO at 16#BC# range 4..4;
TWCR_TWWC at 16#BC# range 3..3; TWCR_TWEN at 16#BC# range 2..2;
TWCR_TWIE at 16#BC# range 0..0;
-- 16#BD#
TWAMR_TWAM at 16#BD# range 1..7;
-- -----------------------------------------------------------------------------
-- PAGE 531 NOTICE 8271B-AVR
-- -----------------------------------------------------------------------------
-- 16#C0#
UCSR0A_RXC0 at 16#C0# range 7..7; UCSR0A_TXC0 at 16#C0# range 6..6;
UCSR0A_UDRE0 at 16#C0# range 5..5; UCSR0A_FE0 at 16#C0# range 4..4;
UCSR0A_DOR0 at 16#C0# range 3..3; UCSR0A_UPE0 at 16#C0# range 2..2;
UCSR0A_U2X0 at 16#C0# range 1..1; UCSR0A_MPCM0 at 16#C0# range 0..0;
-- 16#C1#
UCSR0B_RXCIE0 at 16#C1# range 7..7; UCSR0B_TXCIE0 at 16#C1# range 6..6;
UCSR0B_UDRIE0 at 16#C1# range 5..5; UCSR0B_RXEN0 at 16#C1# range 4..4;
UCSR0B_TXEN0 at 16#C1# range 3..3; UCSR0B_UCSZ02 at 16#C1# range 2..2;
UCSR0B_RXB80 at 16#C1# range 1..1; UCSR0B_TXB80 at 16#C1# range 0..0;
-- 16#C2#
UCSR0C_UMSEL0 at 16#C2# range 6..7; UCSR0C_UPM0 at 16#C2# range 4..5;
UCSR0C_USBS0 at 16#C2# range 3..3; UCSR0C_UCSZ0 at 16#C2# range 1..2;
UCSR0C_UCPOL0 at 16#C2# range 0..0;
-- 16#C4#
UBRR at 16#C4# range 0..11;
-- 16#C6#
UDR0 at 16#C6# range 0..7;
-- OUF !!
end record;
pragma PACK( RAM_MAP );
REG : RAM_MAP; for REG'ADDRESS use 0;
procedure VECT_1; pragma EXPORT ( C, VECT_1, "__vector_1" );
procedure VECT_2; pragma EXPORT ( C, VECT_2, "__vector_2" );
procedure VECT_3; pragma EXPORT ( C, VECT_3, "__vector_3" );
procedure VECT_4; pragma EXPORT ( C, VECT_4, "__vector_4" );
procedure VECT_5; pragma EXPORT ( C, VECT_5, "__vector_5" );
procedure VECT_6; pragma EXPORT ( C, VECT_6, "__vector_6" );
procedure VECT_7; pragma EXPORT ( C, VECT_7, "__vector_7" );
procedure VECT_8; pragma EXPORT ( C, VECT_8, "__vector_8" );
procedure VECT_9; pragma EXPORT ( C, VECT_9, "__vector_9" );
procedure VECT_10; pragma EXPORT ( C, VECT_10, "__vector_10" );
procedure VECT_12; pragma EXPORT ( C, VECT_12, "__vector_12" );
procedure VECT_13; pragma EXPORT ( C, VECT_13, "__vector_13" );
procedure VECT_14; pragma EXPORT ( C, VECT_14, "__vector_14" );
procedure VECT_15; pragma EXPORT ( C, VECT_15, "__vector_15" );
procedure VECT_16; pragma EXPORT ( C, VECT_16, "__vector_16" );
procedure VECT_17; pragma EXPORT ( C, VECT_17, "__vector_17" );
procedure VECT_20; pragma EXPORT ( C, VECT_20, "__vector_20" );
procedure VECT_21; pragma EXPORT ( C, VECT_21, "__vector_21" );
procedure VECT_22; pragma EXPORT ( C, VECT_22, "__vector_22" );
procedure VECT_23; pragma EXPORT ( C, VECT_23, "__vector_23" );
procedure VECT_25; pragma EXPORT ( C, VECT_25, "__vector_25" );
-----------
end ATMEGA_328P;
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-- 1 2 3 4 5 6 7 8 9 0 1 2
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